Single transistor non-volatile electrically alterable memory devices where bits can be individually programmed but collectively erased are known as flash EPROM memory devices. A representative example now in production is described in U.S. Pat. No. 5,242,848. The floating gate of the flash cell as taught in that patent disclosure is strongly coupled with the deep diffusion of the bit line, but is only weakly coupled to the word line through a thick LOCOS oxide grown on the floating gate. The polysilicon word line serves as an erase line at the bird's beak of the floating gate and also as a select gate which allows for programming by source-side injection.
Such a cell design, although viable, has a number of short comings. The large lateral drain diffusion needed for coupling requires a large fraction of the cell area, leaving only a small channel length to the floating gate for control of the channel. Since the field oxide edges can not be self-aligned to any of the gates, allowances must be made for misalignment, variations in diffusion line width and select gate length, and waste in cell area. All these features make it difficult to scale the device down, especially in the deep sub-micron regime where dimensional uncertainty must comprise only a small fraction of the overall geometry.
Therefore, it would be desirable to have a method for manufacturing of EPROM memory cells that is scaleable to deep-submicron levels using self alignment techniques and have a resulting memory array that requires low current for programming the memory cells.